SemiAnalysis: The Great AI Silicon Shortage#
| URL | https://newsletter.semianalysis.com/p/the-great-ai-silicon-shortage |
| Published | 2026-03-12 |
| Read | 2026-09-26 (free section only) |
| Paywall | The data-centre and power constraint sections |
Summary (our words)#
The binding constraint on AI hardware has moved from CoWoS packaging to TSMC N3 logic wafers:
- AI takes about 60% of N3 output in 2026 and about 86% in 2027. Effective N3 utilisation passes 100% in the second half of 2026, and TSMC can't add enough for two years.
- Blackwell (4NP) ships in higher 2026 volume than Rubin (N3P) because its supply chain is more mature.
- Weakening smartphone demand could free N3 wafers for AI.
- HBM is the next constraint, at about 3× the wafer of commodity DRAM, worse with HBM4 and HBM4E.
- Google's 2026 capex expectation roughly doubled, and hyperscalers would spend more if silicon allowed.
Claims#
| ID | Claim | Evidence |
|---|---|---|
| SA-silicon-1 | TSMC N3 is the binding constraint; CoWoS is now secondary | "We are now firmly in the silicon shortage phase." |
| SA-silicon-2 | AI is about 60% of N3 in 2026 and about 86% in 2027; consumer electronics largely squeezed out | Free section |
| SA-silicon-3 | Effective N3 utilisation passes 100% in 2H 2026; TSMC can't meet demand for two years | Free section |
| SA-silicon-4 | Rubin moves Nvidia from 4NP to N3P; Blackwell outships Rubin in 2026 | Free section |
| SA-silicon-5 | HBM uses about 3× the wafer of commodity DRAM; HBM4 and HBM4E worsen the ratio | "HBM consumes roughly three times more wafer capacity than commodity DRAM" |
| SA-silicon-6 | Smartphone units fall by low double digits year on year | Free section |
| SA-silicon-7 | Google's 2026 capex expectation roughly doubled against earlier expectations | Free section |
Our notes#
- SA-silicon-2 gives a physical reason for the RTX 60 delay. A Rubin-generation consumer die needs N3, and N3 has no room in 2027.
- SA-silicon-4 cuts the other way for the 5090. GB202 is on the 4N family. As Nvidia's data-centre volume moves to N3, 4N pressure eases, so wafers aren't what limits the 5090; GDDR7 and Nvidia's allocation are.