RTX 5090 node motherboard and PCIe lane decision#

Status: Reference Last verified: 2026-09-26 Canonical for: motherboard choice, CPU lane budget, M.2 slot layout, GPU link width and the onboard-versus-add-in 10GbE path for the RTX 5090 nodes (PC1, PC2, PC3)

Consolidated from the pre-order IdealTech decision (2026-09-22/23), the platform sections of the earlier overview, and the node decision record (2026-09-24). Prices are the IdealTech list of 2026-09-22 unless stated.

Decision#

Every node uses the MSI MAG X870E Tomahawk Max WiFi with a Ryzen 9 9950X:

• The RTX 5090 keeps a CPU PCIe 5.0 x16 link.
• Two independent CPU PCIe 5.0 x4 M.2 slots carry the model drive and the OS drive.
• Onboard 5GbE serves the NAS. 10GbE, if ever justified, is an add-in NIC on chipset lanes, not a new board.

It cost RM450 more than the promotion's MSI PRO X870E-S EVO. That buys the second CPU-connected Gen5 M.2 slot and a widely deployed, well-validated board. No AM5 board offers anything this design needs beyond it.

The lane budget#

AMD specifies 28 native lanes on the 9950X, 24 usable for devices; the other four are the chipset uplink. Every AM5 CPU, X3D included, has the same I/O model, so a different AM5 CPU cannot add lanes. The Tomahawk makes the best allocation available:

Ryzen 9 9950X, 24 usable device lanes
├── 16  PCI_E1  ── RTX 5090, PCIe 5.0 x16
├──  4  M2_1    ── dedicated CPU NVMe path
└──  4  M2_2    ── general-purpose path, shared with rear USB4
chipset (behind the x4 uplink)
├── M2_3, M2_4  ── PCIe 4.0 x4 each
├── PCI_E2      ── PCIe 3.0 x1
└── PCI_E3      ── PCIe 4.0 x4

A GPU at x16 plus three CPU-direct x4 drives would need 28 device lanes, which AM5 cannot supply. No BIOS update, chipset or premium VRM creates the missing four.

Slot layout as ordered#

M2_2 must be set to x4 in the BIOS. On the Tomahawk, M2_2 shares its four lanes with the rear USB4 controller. With both enabled, each gets x2; selecting full x4 for M2_2 disables the rear 40 Gbps USB-C ports (MSI specification). USB4 has no role on a service node, so take x4. The GPU link is unaffected either way. PC2 can leave USB4 enabled until its OS drive arrives.

If the model cache ever outgrows 2 TB, put further drives in the chipset Gen4 slots and split model families across them rather than striping. The loader never realised more than about 4.6 GiB/s in a workload, well under a Gen4 x4 link (node record). The two SSDs and a future NIC share the chipset uplink, which is fine for OS, output and cache-fill traffic.

Why the Tomahawk Max and not the included PRO X870E-S EVO#

The PRO X870E-S EVO has one CPU-connected Gen5 x4 M.2 slot, chipset Gen4 slots, onboard 5GbE and a Gen5 x16 GPU slot. It would run one model drive with the OS on a chipset slot, which is what the pre-order plan assumed. The ordered builds put the OS drive on the second CPU slot, which only the Tomahawk provides without touching the GPU's lanes.

The board choice also follows the fleet's popular-parts rule. As of 2026-09-24, G.Skill's validation list did not include the new PRO X870E-S EVO, and TeamGroup had validated two kits on it against nine on the Tomahawk Max. The Tomahawk line is widely deployed, so BIOS issues and failure modes are known and later debugging is easier. One board across PC1–PC3 means one BIOS configuration and one spare-parts set.

GPU link width: why x16, and how much it matters#

The RTX 5090 has a PCIe 5.0 x16 host interface. Halving the link to x8 does not disable CUDA cores, reduce the 32 GB of VRAM or slow the card's internal GDDR7. It does halve host-to-device bandwidth:

That link carries model upload, CPU offload, spilled tensors and streamed transfers. During purchasing the founder told the agents to keep x16, so the pre-order docs treat it as a hard requirement. It is not one now. Three RTX 5090 hosts ran at Gen5 x8 with warm floors in the normal 575–600 W range and small cold penalties: machine 137184 (7.28 s MiniMax penalty, 26.9 GiB/s pinned H2D), 143669 (7.09 s) and 56934 (5.60 s) (multivariable journal). The storage reader, not the GPU link, was the tighter limit on those paths. These are cross-host observations (137184 and 56934 were one GPU of a two-GPU host), not a same-machine x8/x16 test.

The ordered nodes run at x16 because the Tomahawk gives it for free alongside two CPU M.2 slots. x8 is an acceptable trade when it buys something real, such as a third CPU-direct drive, a cheaper board or a second card. Nothing in the current design needs that, so no trade is being made. Before relying on x8 in production, run the node's own cold/warm suite and pinned H2D at x8, since the evidence above is cross-host. Lane width is also not why each node has one GPU; the reasons there are RAM, cooling, failure isolation and how the cards were sold (node record).

Boards and platforms rejected#

AM5 boards with three CPU M.2 sockets#

Several AM5 boards expose three CPU-connected Gen5 M.2 sockets by bifurcating the GPU's 16 lanes. Populating the extra sockets drops the GPU to x8. They were rejected under the keep-x16 instruction. With x8 now acceptable, they remain the way to get a third CPU-direct drive on AM5, but every one costs more than the Tomahawk for a slot the design does not use. Manufacturer lane tables, not retailer descriptions, decide:

Sources: Aorus Elite, Aorus Master, B850-E, Crosshair Hero, Godlike. The retailer list also over-counts: the Aorus Master X3D, Aorus Elite X3D Ice, Aero X3D Wood, ASUS X870E Dark Hero and X870E-E Gaming WiFi7 Neo are listed with three Gen5 M.2 sockets, but their manufacturer specifications show two CPU Gen5 paths.

Threadripper#

A third CPU-direct Gen5 path while keeping x16 needs Threadripper (or a bifurcating AM5 board above, at x8). The cheapest lane-correct option on the list was a Threadripper 9960X (RM7,399, 88 usable lanes) on a Gigabyte TRX50 AERO D (RM3,099, three CPU Gen5 x4 M.2 plus one CPU Gen4). That is RM5,800 more than the 9950X and Tomahawk before ECC RDIMMs (price on request), an sTR5 cooler and a 350 W CPU's power and cooling. ComfyUI averages under two CPU cores, so the only thing it would buy is a third CPU M.2 slot, which the design does not need. Revisit only for a measured workload that needs the lanes.

Networking: onboard 5GbE, add-in 10GbE later#

The board's port is 5 Gbit/s Ethernet, about 500–550 MB/s in practice. One NAS hard drive fills a cache at roughly 190–220 MB/s, and prefetch hides fills from jobs, so 5GbE is not the bottleneck. Moving the 42.47 GB MiniMax set takes about 68 s at 5 Gbit/s and 34 s at 10 Gbit/s, before overheads. Neither is a substitute for local NVMe, which reads the same set in seconds.

If measured cache-fill traffic ever saturates 5GbE, add a NIC rather than change the board:

• The TP-Link TX401 (RM499) is PCIe 3.0 x4, 10GBASE-T, with Linux support. It goes in PCI_E3 (chipset PCIe 4.0 x4); PCI_E2 is x1 and too narrow. It uses no CPU lanes, so the GPU and both CPU M.2 slots are unaffected.
• It suits an RJ45 switch. For an SFP+ switch, buy a Linux-supported SFP+ NIC and DAC or fibre instead.
• A NIC can be replaced or RMAed without touching the motherboard.
• Dry-fit it first. Install the actual GPU in PCI_E1 and the NIC in PCI_E3. Accept only if the NIC seats normally, the bracket aligns, the GPU support does not interfere, and the NIC does not touch the GPU or block its fans. The Zotac Solid OC is 3.5 slots thick. Moving the GPU to a slot that drops it to x8 is acceptable if the node's own suite shows no loss, but try the case and slot layout first.

Boards with onboard 10GbE cost more and mostly fail the storage topology:

Paying RM1,900–2,800 to integrate a replaceable RM499 function buys no ComfyUI throughput or availability.

Acceptance checks#

With every intended device installed, on each node:

• The RTX 5090 negotiates its intended width under load, x16 on the Tomahawk (an idle link can downtrain; check with the GPU busy). An unexpected x8 is a fault to explain, even though x8 itself is acceptable.
• Both M.2 drives negotiate 32.0 GT/s x4 and enumerate under CPU root ports, not the chipset. On a default BIOS, M2_2 shows x2 until it is set to x4.
• Pinned host-to-device bandwidth is measured, not inferred; the healthy x16 hosts measured about 44–54 GiB/s. A host at 3.4 GiB/s had a normal warm floor but a 20 s cold penalty.
• If a NIC is fitted later, the GPU and both CPU M.2 links still show the same widths.

The rest of the node acceptance suite is in the node record.